@Override
public Value visitADD_SUB(Verilog2001Parser.ADD_SUBContext ctx) {
// System.out.println("+-");
Value left = visit(ctx.expression(0));
Value right = visit(ctx.expression(1));
int mask1 = (1 << left.getSize()) - 1;
int mask2 = (1 << right.getSize()) - 1;
switch (ctx.op.getType()) {
case (Verilog2001Parser.SUB):
{
return new Value(
Integer.valueOf(left.asInt() - right.asInt()), (mask1 >= mask2) ? mask1 : mask2);
}
case (Verilog2001Parser.ADD):
{
return new Value(
Integer.valueOf(left.asInt() + right.asInt()), (mask1 >= mask2) ? mask1 : mask2);
}
default:
{
System.out.println("Error: Not ADD SUB called: " + ctx.getText());
}
}
return null;
}
@Override
public Value visitFCASE_ITEM(Verilog2001Parser.FCASE_ITEMContext ctx) {
Value constant_expression = visit(ctx.expression());
if (constant_expression.asInt() == case_expression.asInt()) {
visit(ctx.statement());
return new Value(true);
}
return new Value(false);
}
@Override
public Value visitBIT_ACCESS(Verilog2001Parser.BIT_ACCESSContext ctx) {
String ident = ctx.identifier().getText();
ParsePort port = hash_ports.get(ident);
ParseRegWire regWire = hash_vars.get(ident);
Value number = visit(ctx.constant_expression());
if (regWire != null) {
int value_of_bit = regWire.getIntegerBit(number.asInt(), old_val_idx);
// System.out.println("RegWire bit:"+ident+" loc: "+number.asInt()+" val:"+value_of_bit);
return new Value(value_of_bit, 1);
} else if (port != null) {
int value_of_bit = port.getIntegerBit(number.asInt(), old_val_idx);
// System.out.println("Port bit:"+ident+" loc: "+number.asInt()+" val:"+value_of_bit);
return new Value(value_of_bit, 1);
}
System.out.println("Error: No item called: " + ident);
return visitChildren(ctx);
}
@Override
public Value visitMULT_DIV_MOD(Verilog2001Parser.MULT_DIV_MODContext ctx) {
// System.out.println("*/%");
Value left = visit(ctx.expression(0));
Value right = visit(ctx.expression(1));
int mask1 = (1 << left.getSize()) - 1;
int mask2 = (1 << right.getSize()) - 1;
switch (ctx.op.getType()) {
case (Verilog2001Parser.MULT):
{
return new Value(
Integer.valueOf(left.asInt() * right.asInt()),
(mask1 >= mask2) ? 2 * mask1 : 2 * mask2);
}
case (Verilog2001Parser.DIV):
{
return new Value(
Integer.valueOf(left.asInt() / right.asInt()), (mask1 >= mask2) ? mask1 : mask2);
}
case (Verilog2001Parser.MOD):
{
return new Value(
Integer.valueOf(left.asInt() % right.asInt()), (mask1 >= mask2) ? mask1 : mask2);
}
default:
{
System.out.println("Error: Not ADD SUB called: " + ctx.getText());
}
}
return null;
}
/* --------------------------------------------------------------------------
* -----------
* --------------------------------------------------------------
* -------------------------- Handle assignment statements
* ------------------
* ----------------------------------------------------------------------
* ----
* ----------------------------------------------------------------------
* ------------ */
@Override
public Value visitVariable_lvalue(Verilog2001Parser.Variable_lvalueContext ctx) {
String ident = ctx.identifier().getText();
ParsePort port = hash_ports.get(ident);
ParseRegWire regWire = hash_vars.get(ident);
Value Size = null;
if (ctx.range_expression() != null) {
/* Visit the decimal number ... NOTE range is not done here! */
Size = visit(ctx.range_expression().decimal_number());
}
if (regWire != null) {
return new Value(ValueType.REG_WIRE_T, null, regWire, (Size != null ? Size.asInt() : -1));
} else if (port != null) {
return new Value(ValueType.PORT_T, port, null, (Size != null ? Size.asInt() : -1));
}
System.out.println("Error: No left hand side called: " + ident);
return null;
}
@Override
public Value visitContinuous_assign(Verilog2001Parser.Continuous_assignContext ctx) {
// System.out.println("Continuous Visit:"+ctx.getText()+" Line:"+ctx.start.getLine());
Value left = visit(ctx.variable_lvalue());
Value right = visit(ctx.expression());
/* Update the data structure with the right value */
left.setVar(new_val_idx, right.asInt(), cycle_time);
// System.out.println("Continuous assign:"+left.getVarName()+" Value = "+right.asInt());
return null;
}
/* --------------------------------------------------------------------------
* -----------
* --------------------------------------------------------------
* -------------------------- Handle statements
* ------------------------------
* ----------------------------------------------------------
* ----------------
* ---------------------------------------------------------------------- */
@Override
public Value visitBlocking_assignment(Verilog2001Parser.Blocking_assignmentContext ctx) {
if (!is_combinational) {
System.out.println("ERROR: Blocking Statement in a sequential block");
return new Value(false);
}
// System.out.println("Visit:"+ctx.getText()+" Line:"+ctx.start.getLine());
Value left = visit(ctx.variable_lvalue());
Value right = visit(ctx.expression());
/* Update the data structure with the right value */
left.setVar(new_val_idx, right.asInt(), cycle_time);
// System.out.println("AssignBlocking:"+left.getVarName()+" Value = "+right.asInt());
return null;
}
@Override
public Value visitNonblocking_assignment(Verilog2001Parser.Nonblocking_assignmentContext ctx) {
if (is_sequential_sim_cycle) {
/* Only store on simulate cycles */
if (!is_sequential) {
System.out.println("ERROR: Non Blocking Statement in a combinational block");
return new Value(false);
}
// System.out.println("Visit:"+ctx.getText());
Value left = visit(ctx.variable_lvalue());
Value right = visit(ctx.expression());
/* Update the data structure with the right value */
left.setVar(new_val_idx, right.asInt(), cycle_time);
// System.out.println("AssignNonBlocking:"+left.getVarName()+" Value = "+right);
}
return null;
}
@Override
public Value visitCOMPARES(Verilog2001Parser.COMPARESContext ctx) {
Value left = visit(ctx.expression(0));
Value right = visit(ctx.expression(1));
switch (ctx.op.getType()) {
case (Verilog2001Parser.NOTEQUAL):
{
return new Value(Boolean.valueOf(left.asInt() != right.asInt()));
}
case (Verilog2001Parser.EQUAL):
{
return new Value(Boolean.valueOf(left.asInt() == right.asInt()));
}
case (Verilog2001Parser.LT):
{
return new Value(Boolean.valueOf(left.asInt() < right.asInt()));
}
case (Verilog2001Parser.LTE):
{
return new Value(Boolean.valueOf(left.asInt() <= right.asInt()));
}
case (Verilog2001Parser.GT):
{
return new Value(Boolean.valueOf(left.asInt() > right.asInt()));
}
case (Verilog2001Parser.GTE):
{
return new Value(Boolean.valueOf(left.asInt() >= right.asInt()));
}
default:
{
System.out.println("Error: No lofical operator called: " + ctx.getText());
}
}
return null;
}
@Override
public Value visitBLOGIC(Verilog2001Parser.BLOGICContext ctx) {
// System.out.println("Binary Logic");
Value left = visit(ctx.expression(0));
Value right = visit(ctx.expression(1));
int mask1 = (1 << left.getSize()) - 1;
int mask2 = (1 << right.getSize()) - 1;
switch (ctx.op.getType()) {
case (Verilog2001Parser.BITWISE_AND):
{
return new Value(
Integer.valueOf(left.asInt() & right.asInt()), (mask1 >= mask2) ? mask1 : mask2);
}
case (Verilog2001Parser.BITWISE_NAND):
{
return new Value(
Integer.valueOf(~(left.asInt() & right.asInt())), (mask1 >= mask2) ? mask1 : mask2);
}
case (Verilog2001Parser.BITWISE_OR):
{
return new Value(
Integer.valueOf(left.asInt() | right.asInt()), (mask1 >= mask2) ? mask1 : mask2);
}
case (Verilog2001Parser.BITWISE_NOR):
{
return new Value(
Integer.valueOf(~(left.asInt() | right.asInt())), (mask1 >= mask2) ? mask1 : mask2);
}
case (Verilog2001Parser.BITWISE_XOR):
{
return new Value(
Integer.valueOf(left.asInt() ^ right.asInt()), (mask1 >= mask2) ? mask1 : mask2);
}
case (Verilog2001Parser.BITWISE_XNOR):
{
return new Value(
Integer.valueOf(~(left.asInt() ^ right.asInt())), (mask1 >= mask2) ? mask1 : mask2);
}
case (Verilog2001Parser.SHIFT_LEFT):
{
return new Value(
Integer.valueOf(left.asInt() << right.asInt()), (mask1 >= mask2) ? mask1 : mask2);
}
case (Verilog2001Parser.SHIFT_RIGHT):
{
return new Value(
Integer.valueOf(left.asInt() >> right.asInt()), (mask1 >= mask2) ? mask1 : mask2);
}
default:
{
System.out.println("Error: No Binary operator called: " + ctx.getText());
}
}
return null;
}
@Override
public Value visitUNOT(Verilog2001Parser.UNOTContext ctx) {
// System.out.println("UNOT");
Value unary = visit(ctx.expression());
return new Value(Integer.valueOf(~unary.asInt()));
}
