public static void emitRegReg( CompilationResultBuilder crb, SPARCMacroAssembler masm, SPARCArithmetic opcode, Value dst, Value src1, Value src2, LIRFrameState info, SPARCDelayedControlTransfer delaySlotLir) { int exceptionOffset = -1; assert !isConstant(src1) : src1; assert !isConstant(src2) : src2; switch (opcode) { case IADD: delaySlotLir.emitControlTransfer(crb, masm); new Add(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case ISUB: delaySlotLir.emitControlTransfer(crb, masm); new Sub(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case IMUL: delaySlotLir.emitControlTransfer(crb, masm); new Mulx(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case IDIV: new Signx(asIntReg(src1), asIntReg(src1)).emit(masm); new Signx(asIntReg(src2), asIntReg(src2)).emit(masm); delaySlotLir.emitControlTransfer(crb, masm); exceptionOffset = masm.position(); new Sdivx(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case IUDIV: new Signx(asIntReg(src1), asIntReg(src1)).emit(masm); new Signx(asIntReg(src2), asIntReg(src2)).emit(masm); delaySlotLir.emitControlTransfer(crb, masm); exceptionOffset = masm.position(); new Udivx(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case IAND: delaySlotLir.emitControlTransfer(crb, masm); new And(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case IOR: delaySlotLir.emitControlTransfer(crb, masm); new Or(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case IXOR: delaySlotLir.emitControlTransfer(crb, masm); new Xor(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case ISHL: delaySlotLir.emitControlTransfer(crb, masm); new Sll(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case ISHR: delaySlotLir.emitControlTransfer(crb, masm); new Sra(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case IUSHR: delaySlotLir.emitControlTransfer(crb, masm); new Srl(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm); break; case IREM: throw GraalInternalError.unimplemented(); case LADD: delaySlotLir.emitControlTransfer(crb, masm); new Add(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm); break; case LSUB: delaySlotLir.emitControlTransfer(crb, masm); new Sub(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm); break; case LMUL: delaySlotLir.emitControlTransfer(crb, masm); new Mulx(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm); break; case LDIV: delaySlotLir.emitControlTransfer(crb, masm); exceptionOffset = masm.position(); new Sdivx(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm); break; case LUDIV: delaySlotLir.emitControlTransfer(crb, masm); exceptionOffset = masm.position(); new Udivx(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm); break; case LAND: delaySlotLir.emitControlTransfer(crb, masm); new And(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm); break; case LOR: delaySlotLir.emitControlTransfer(crb, masm); new Or(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm); break; case LXOR: delaySlotLir.emitControlTransfer(crb, masm); new Xor(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm); break; case LSHL: delaySlotLir.emitControlTransfer(crb, masm); new Sllx(asLongReg(src1), asIntReg(src2), asLongReg(dst)).emit(masm); break; case LSHR: delaySlotLir.emitControlTransfer(crb, masm); new Srax(asLongReg(src1), asIntReg(src2), asLongReg(dst)).emit(masm); break; case LUSHR: delaySlotLir.emitControlTransfer(crb, masm); new Srlx(asLongReg(src1), asIntReg(src2), asLongReg(dst)).emit(masm); break; case FADD: delaySlotLir.emitControlTransfer(crb, masm); new Fadds(asFloatReg(src1), asFloatReg(src2), asFloatReg(dst)).emit(masm); break; case FSUB: delaySlotLir.emitControlTransfer(crb, masm); new Fsubs(asFloatReg(src1), asFloatReg(src2), asFloatReg(dst)).emit(masm); break; case FMUL: delaySlotLir.emitControlTransfer(crb, masm); if (dst.getPlatformKind() == Kind.Double) { new Fsmuld(asFloatReg(src1), asFloatReg(src2), asDoubleReg(dst)).emit(masm); } else if (dst.getPlatformKind() == Kind.Float) { new Fmuls(asFloatReg(src1), asFloatReg(src2), asFloatReg(dst)).emit(masm); } break; case FDIV: delaySlotLir.emitControlTransfer(crb, masm); exceptionOffset = masm.position(); new Fdivs(asFloatReg(src1), asFloatReg(src2), asFloatReg(dst)).emit(masm); break; case FREM: throw GraalInternalError.unimplemented(); case DADD: delaySlotLir.emitControlTransfer(crb, masm); new Faddd(asDoubleReg(src1), asDoubleReg(src2), asDoubleReg(dst)).emit(masm); break; case DSUB: delaySlotLir.emitControlTransfer(crb, masm); new Fsubd(asDoubleReg(src1), asDoubleReg(src2), asDoubleReg(dst)).emit(masm); break; case DMUL: delaySlotLir.emitControlTransfer(crb, masm); new Fmuld(asDoubleReg(src1), asDoubleReg(src2), asDoubleReg(dst)).emit(masm); break; case DDIV: delaySlotLir.emitControlTransfer(crb, masm); exceptionOffset = masm.position(); new Fdivd(asDoubleReg(src1), asDoubleReg(src2), asDoubleReg(dst)).emit(masm); break; case DREM: throw GraalInternalError.unimplemented(); case DAND: delaySlotLir.emitControlTransfer(crb, masm); new Fandd(asDoubleReg(src1), asDoubleReg(src2), asDoubleReg(dst)).emit(masm); break; default: throw GraalInternalError.shouldNotReachHere(); } if (info != null) { assert exceptionOffset != -1; crb.recordImplicitException(exceptionOffset, info); } }