public SignExtend(UnaryOp cast) {
Iterator<Port> ports = cast.getDataPorts().iterator();
Port d_port = ports.next();
assert (d_port.isUsed()) : "Operand port in unary operation is set to unused.";
Bus d_bus = d_port.getBus();
assert (d_bus != null) : "Operand port in unary operation not attached to a bus.";
PortWire pwire = new PortWire(d_port);
if (pwire.getExpression() instanceof BaseNumber) {
// input is a constant value, so the resize should be a no-op?
} else {
if (pwire.getExpression() instanceof Wire) {
operand = (Wire) pwire.getExpression();
} else {
operand =
new Wire(ID.toVerilogIdentifier(ID.showLogical(cast)), d_port.getValue().getSize());
add(new Assign.Continuous(operand, new PortWire(d_port)));
produced_nets.add(operand);
}
result_wire = NetFactory.makeNet(cast.getResultBus());
produced_nets.add(result_wire);
int result_width = result_wire.getWidth();
/** unsigned value will be padded with zeros * */
add(
new Assign.Continuous(
result_wire,
new org.xronos.openforge.verilog.pattern.SignExtend(operand, result_width)));
}
}
private static String getVerilogName(Object obj) {
return ID.toVerilogIdentifier(ID.showLogical(obj));
}