/** Creates the instantiation and connects up all the ports/buses. */
public void stateLogic(Module module, StateMachine mach) {
ModuleInstance instance = new ModuleInstance(getVerilogName(design), "test");
/*
* Connect clock and reset if needed.
*/
for (Design.ClockDomain domain : design.getAllocatedClockDomains()) {
instance.add(
new PortConnection(new Input(getVerilogName(domain.getClockPin()), 1), mach.getClock()));
if (domain.getResetPin() != null) {
instance.add(
new PortConnection(
new Input(getVerilogName(domain.getResetPin()), 1), mach.getReset()));
}
}
for (TaskHandle th : taskHandles) {
Task task = th.getTask();
for (Port port : task.getCall().getPorts()) {
InputPin pin = (InputPin) design.getPin(port);
Wire portWire = th.getWireForConnection(port);
if (portWire == null) {
continue;
}
// Use the Port's bus to agree with InputPinPort and
// VerilogNamer, but output pins use the actual pin.
PortConnection pc =
new PortConnection(new Input(getVerilogName(pin.getBus()), pin.getWidth()), portWire);
instance.add(pc);
}
for (Bus bus : task.getCall().getExit(Exit.DONE).getBuses()) {
Wire busWire = th.getWireForConnection(bus);
if (busWire == null) {
continue;
}
Pin pin = design.getPin(bus);
PortConnection pc =
new PortConnection(new Output(getVerilogName(pin), pin.getWidth()), busWire);
instance.add(pc);
}
Pin goPin = design.getPin(task.getCall().getGoPort());
if (goPin != null) {
instance.add(
new PortConnection(
new Input(getVerilogName(((InputPin) goPin).getBus()), 1), th.getGoWire()));
}
Pin donePin = design.getPin(task.getCall().getExit(Exit.DONE).getDoneBus());
if (donePin != null) {
instance.add(new PortConnection(new Output(getVerilogName(donePin), 1), th.getDoneWire()));
}
}
module.state(instance);
}
