Example #1
0
    public SignExtend(UnaryOp cast) {
      Iterator<Port> ports = cast.getDataPorts().iterator();
      Port d_port = ports.next();
      assert (d_port.isUsed()) : "Operand port in unary operation is set to unused.";
      Bus d_bus = d_port.getBus();
      assert (d_bus != null) : "Operand port in unary operation not attached to a bus.";
      PortWire pwire = new PortWire(d_port);
      if (pwire.getExpression() instanceof BaseNumber) {
        // input is a constant value, so the resize should be a no-op?
      } else {
        if (pwire.getExpression() instanceof Wire) {
          operand = (Wire) pwire.getExpression();
        } else {
          operand =
              new Wire(ID.toVerilogIdentifier(ID.showLogical(cast)), d_port.getValue().getSize());
          add(new Assign.Continuous(operand, new PortWire(d_port)));
          produced_nets.add(operand);
        }

        result_wire = NetFactory.makeNet(cast.getResultBus());
        produced_nets.add(result_wire);

        int result_width = result_wire.getWidth();

        /** unsigned value will be padded with zeros * */
        add(
            new Assign.Continuous(
                result_wire,
                new org.xronos.openforge.verilog.pattern.SignExtend(operand, result_width)));
      }
    }
Example #2
0
 /** Graphs the incoming connections to a component's ports. */
 protected void graphEdges(Component component, Bus src) {
   ComponentNode componentNode = (ComponentNode) nodeMap.get(component);
   graphEdge(componentNode, component.getGoPort());
   for (org.xronos.openforge.lim.Port port : component.getDataPorts()) {
     if (port.getBus() == src) {
       graphEdge(componentNode, port);
     }
   }
 }
Example #3
0
    Output(OutputPin opin, int nodeCount, int fontSize) {
      super(ID.showLogical(opin), nodeCount, fontSize);
      _graph.ln("Output Pin: " + opin);
      graph(opin, nodeCount++);
      Port p = opin.getPort();
      Bus b = p.getBus();
      graph(b.getOwner().getOwner(), nodeCount++);

      graphEdges(opin);
    }
Example #4
0
 private boolean findUnknownGateDepthOnInputs(Component component) {
   for (Port port : component.getPorts()) {
     // assert (port.isConnected() &&
     // this.exitToGateDepthMap.containsKey(port.getBus().getOwner()));
     if (port.isConnected() && !exitToGateDepthMap.containsKey(port.getBus().getOwner())) {
       unresolvedGateDepthComponents.push(component);
       return true;
     }
   }
   return false;
 }
Example #5
0
 private int getMaxInputGateDepth(Component component) {
   int maxGateDepth = 0;
   component = (component instanceof InBuf) ? component.getOwner() : component;
   for (Port port : component.getPorts()) {
     if (port == component.getClockPort() || port == component.getResetPort()) {
       continue;
     }
     int gateDepth =
         port.isConnected() ? exitToGateDepthMap.get(port.getBus().getOwner()).intValue() : 0;
     maxGateDepth = Math.max(maxGateDepth, gateDepth);
   }
   return maxGateDepth;
 }