Ejemplo n.º 1
0
  private String showComponent(Component comp) {
    String ret = comp.toString();
    for (Port port : comp.getPorts()) {
      String value = port.getValue() == null ? "null" : port.getValue().debug();
      if (port == comp.getGoPort() || port == comp.getClockPort() || port == comp.getResetPort()) ;
      else ret = ret + " p:" + value;
      /*
       * if (port == getGoPort()) ret = ret + " go:" + val; else if (port
       * == getClockPort()) ret = ret + " ck:" + val; else if (port ==
       * getResetPort()) ret = ret + " rs:" + val; else ret = ret + " p:"
       * + val;
       */
    }
    for (Exit exit : comp.getExits()) {
      for (Bus bus : exit.getBuses()) {
        String value = bus.getValue() == null ? "null" : bus.getValue().debug();
        if (bus == exit.getDoneBus())
          // ret = ret + " done:" + val;
          ;
        else ret = ret + " data:" + value;
      }
    }

    return ret;
  }
Ejemplo n.º 2
0
    public SignExtend(UnaryOp cast) {
      Iterator<Port> ports = cast.getDataPorts().iterator();
      Port d_port = ports.next();
      assert (d_port.isUsed()) : "Operand port in unary operation is set to unused.";
      Bus d_bus = d_port.getBus();
      assert (d_bus != null) : "Operand port in unary operation not attached to a bus.";
      PortWire pwire = new PortWire(d_port);
      if (pwire.getExpression() instanceof BaseNumber) {
        // input is a constant value, so the resize should be a no-op?
      } else {
        if (pwire.getExpression() instanceof Wire) {
          operand = (Wire) pwire.getExpression();
        } else {
          operand =
              new Wire(ID.toVerilogIdentifier(ID.showLogical(cast)), d_port.getValue().getSize());
          add(new Assign.Continuous(operand, new PortWire(d_port)));
          produced_nets.add(operand);
        }

        result_wire = NetFactory.makeNet(cast.getResultBus());
        produced_nets.add(result_wire);

        int result_width = result_wire.getWidth();

        /** unsigned value will be padded with zeros * */
        add(
            new Assign.Continuous(
                result_wire,
                new org.xronos.openforge.verilog.pattern.SignExtend(operand, result_width)));
      }
    }
Ejemplo n.º 3
0
  public UnaryOpAssignment(UnaryOp uo, boolean checkBalance) {
    Iterator<Port> ports = uo.getDataPorts().iterator();
    Port d_port = ports.next();
    assert (d_port.isUsed()) : "Operand port in unary operation is set to unused.";
    // Bus d_bus = d_port.getBus();
    // assert (d_bus != null) :
    // "Operand port in unary operation not attached to a bus.";
    assert (d_port.getValue() != null) : "Operand port in unary operation does not have a value.";
    operand = new PortWire(d_port);

    result_wire = NetFactory.makeNet(uo.getResultBus());

    add(new Assign.Continuous(result_wire, makeOpExpression(operand), checkBalance));
  }