Ejemplo n.º 1
0
 /** Graphs the incoming connections to a component's ports. */
 protected void graphEdges(Component component, Bus src) {
   ComponentNode componentNode = (ComponentNode) nodeMap.get(component);
   graphEdge(componentNode, component.getGoPort());
   for (org.xronos.openforge.lim.Port port : component.getDataPorts()) {
     if (port.getBus() == src) {
       graphEdge(componentNode, port);
     }
   }
 }
Ejemplo n.º 2
0
  /**
   * Completes RegisterRead and RegisterWrite connections passed up to the top-level as side-band
   * ports and buses.
   *
   * @param design the Design which has Registers
   * @param frame the ConnectionFrame which describes the read/write connections
   */
  private void connectGlobalRegisters(Design design, ConnectionFrame frame) {
    // boolean isLittleEndian = EngineThread.getGenericJob()
    // .getUnscopedBooleanOptionValue(OptionRegistry.LITTLE_ENDIAN);

    for (Register register : design.getRegisters()) {
      List<Connection> readList = frame.getReadConnections(register);
      List<Connection> writeList = frame.getWriteConnections(register);

      if (readList.isEmpty() && writeList.isEmpty()) {
        continue;
      }

      Component regPhys = register.makePhysicalComponent(readList, writeList);
      if (register.getInputSwapper() != null) {
        design.getDesignModule().addComponent(register.getInputSwapper());
      }
      design.getDesignModule().addComponent(regPhys);
      if (register.getOutputSwapper() != null) {
        design.getDesignModule().addComponent(register.getOutputSwapper());
      }

      assert regPhys != null;

      if (!writeList.isEmpty()) {
        final Iterator<Port> writePortIter = regPhys.getDataPorts().iterator();
        for (Iterator<Connection> writeListIter = writeList.iterator(); writeListIter.hasNext(); ) {
          final RegisterWriteConnection writeConn = (RegisterWriteConnection) writeListIter.next();
          if (writeConn != null) {
            assert writePortIter.hasNext() : "Too few ports on register physical (enable)";
            final Port enablePort = writePortIter.next();
            assert writePortIter.hasNext() : "Too few ports on register physical (data)";
            final Port dataPort = writePortIter.next();
            enablePort.setBus(writeConn.getEnable());
            dataPort.setBus(writeConn.getData());
          }
        }
      }

      if (!readList.isEmpty()) {
        Bus registerResultBus = null;
        Exit physicalExit = regPhys.getExit(Exit.DONE);
        registerResultBus = physicalExit.getDataBuses().get(0);

        for (Connection connection : readList) {
          RegisterReadConnection rp = (RegisterReadConnection) connection;
          // The read connetion may be null because we had
          // to pad out the pairs in the connection list for
          // the referee.
          if (rp != null) {
            rp.getDataPort().setBus(registerResultBus);
          }
        }
      }
    }
  }