public static void emitUnary( CompilationResultBuilder crb, SPARCMacroAssembler masm, SPARCArithmetic opcode, Value dst, Value src, LIRFrameState info, SPARCDelayedControlTransfer delaySlotLir) { int exceptionOffset = -1; Label notOrdered = new Label(); switch (opcode) { case INEG: delaySlotLir.emitControlTransfer(crb, masm); new Neg(asIntReg(src), asIntReg(dst)).emit(masm); break; case LNEG: delaySlotLir.emitControlTransfer(crb, masm); new Neg(asLongReg(src), asLongReg(dst)).emit(masm); break; case INOT: delaySlotLir.emitControlTransfer(crb, masm); new Not(asIntReg(src), asIntReg(dst)).emit(masm); break; case LNOT: delaySlotLir.emitControlTransfer(crb, masm); new Not(asLongReg(src), asLongReg(dst)).emit(masm); break; case D2F: delaySlotLir.emitControlTransfer(crb, masm); new Fdtos(asDoubleReg(src), asFloatReg(dst)).emit(masm); break; case L2D: delaySlotLir.emitControlTransfer(crb, masm); new Fxtod(asDoubleReg(src), asDoubleReg(dst)).emit(masm); break; case L2F: delaySlotLir.emitControlTransfer(crb, masm); new Fxtos(asDoubleReg(src), asFloatReg(dst)).emit(masm); break; case I2D: delaySlotLir.emitControlTransfer(crb, masm); new Fitod(asFloatReg(src), asDoubleReg(dst)).emit(masm); break; case I2L: delaySlotLir.emitControlTransfer(crb, masm); new Signx(asIntReg(src), asLongReg(dst)).emit(masm); break; case L2I: delaySlotLir.emitControlTransfer(crb, masm); new Signx(asLongReg(src), asIntReg(dst)).emit(masm); break; case B2L: new Sll(asIntReg(src), 24, asLongReg(dst)).emit(masm); delaySlotLir.emitControlTransfer(crb, masm); new Sra(asLongReg(dst), 24, asLongReg(dst)).emit(masm); break; case B2I: new Sll(asIntReg(src), 24, asIntReg(dst)).emit(masm); delaySlotLir.emitControlTransfer(crb, masm); new Sra(asIntReg(dst), 24, asIntReg(dst)).emit(masm); break; case S2L: new Sll(asIntReg(src), 16, asLongReg(dst)).emit(masm); delaySlotLir.emitControlTransfer(crb, masm); new Sra(asLongReg(dst), 16, asLongReg(dst)).emit(masm); break; case S2I: new Sll(asIntReg(src), 16, asIntReg(dst)).emit(masm); delaySlotLir.emitControlTransfer(crb, masm); new Sra(asIntReg(dst), 16, asIntReg(dst)).emit(masm); break; case I2F: delaySlotLir.emitControlTransfer(crb, masm); new Fitos(asFloatReg(src), asFloatReg(dst)).emit(masm); break; case F2D: delaySlotLir.emitControlTransfer(crb, masm); new Fstod(asFloatReg(src), asDoubleReg(dst)).emit(masm); break; case F2L: new Fcmp(CC.Fcc0, Opfs.Fcmps, asFloatReg(src), asFloatReg(src)).emit(masm); new Fbo(true, notOrdered).emit(masm); new Fstox(asFloatReg(src), asDoubleReg(dst)).emit(masm); new Fsubd(asDoubleReg(dst), asDoubleReg(dst), asDoubleReg(dst)).emit(masm); masm.bind(notOrdered); break; case F2I: new Fcmp(CC.Fcc0, Opfs.Fcmps, asFloatReg(src), asFloatReg(src)).emit(masm); new Fbo(true, notOrdered).emit(masm); new Fstoi(asFloatReg(src), asFloatReg(dst)).emit(masm); new Fitos(asFloatReg(dst), asFloatReg(dst)).emit(masm); new Fsubs(asFloatReg(dst), asFloatReg(dst), asFloatReg(dst)).emit(masm); masm.bind(notOrdered); break; case D2L: new Fcmp(CC.Fcc0, Opfs.Fcmpd, asDoubleReg(src), asDoubleReg(src)).emit(masm); new Fbo(false, notOrdered).emit(masm); new Fdtox(asDoubleReg(src), asDoubleReg(dst)).emit(masm); new Fxtod(asDoubleReg(dst), asDoubleReg(dst)).emit(masm); new Fsubd(asDoubleReg(dst), asDoubleReg(dst), asDoubleReg(dst)).emit(masm); masm.bind(notOrdered); break; case D2I: new Fcmp(CC.Fcc0, Opfs.Fcmpd, asDoubleReg(src), asDoubleReg(src)).emit(masm); new Fbo(true, notOrdered).emit(masm); new Fdtoi(asDoubleReg(src), asFloatReg(dst)).emit(masm); new Fsubs(asFloatReg(dst), asFloatReg(dst), asFloatReg(dst)).emit(masm); new Fstoi(asFloatReg(dst), asFloatReg(dst)).emit(masm); masm.bind(notOrdered); break; case FNEG: delaySlotLir.emitControlTransfer(crb, masm); new Fnegs(asFloatReg(src), asFloatReg(dst)).emit(masm); break; case DNEG: delaySlotLir.emitControlTransfer(crb, masm); new Fnegd(asDoubleReg(src), asDoubleReg(dst)).emit(masm); break; default: throw GraalInternalError.shouldNotReachHere("missing: " + opcode); } if (info != null) { assert exceptionOffset != -1; crb.recordImplicitException(exceptionOffset, info); } }