Esempio n. 1
0
  /**
   * Performs one operation cycle of the instruction in the pipeline stage. The pipeline stage is
   * define by the parameter stage.<br>
   * In Fireworks Three Stage Pipeline processor the instruction only operates in the execute
   * pipeline stage. Because of that the parameter stage in practice is never used.
   *
   * @param stage the pipeline stage where the instruction is operating.
   *     <p>1 - fetch stage.<br>
   *     2 - decode stage.<br>
   *     3 - execute stage.
   * @return the cpu status after the instruction operates the cycle.
   * @see system.cpu.Instruction#Stage(int)
   */
  public final int Stage(int stage) {
    int value;
    int aux_a;
    int aux_b;

    if (cycles < latency) {
      cycles++;
      return cpu_status.STALL;
    }
    cycles = 1;
    aux_a = cpu.getGeneral(rA);
    aux_b = cpu.getGeneral(rB);
    value = (int) ((aux_a * aux_b) >>> 32);
    cpu.putGeneral(rD, value);
    return cpu_status.NORMAL;
  }
Esempio n. 2
0
  /**
   * Performs one operation cycle of the instruction in the pipeline stage. The pipeline stage is
   * define by the parameter stage.<br>
   * In Fireworks Three Stage Pipeline processor the instruction only operates in the execute
   * pipeline stage. Because of that the parameter stage in practice is never used.
   *
   * @param stage the pipeline stage where the instruction is operating.
   *     <p>1 - fetch stage.<br>
   *     2 - decode stage.<br>
   *     3 - execute stage.
   * @return the cpu status after the instruction operates the cycle.
   * @see system.cpu.Instruction#Stage(int)
   */
  public final int Stage(int stage) {
    int msr;

    if (cycles < latency) {
      cycles++;
      return cpu_status.STALL;
    }
    cycles = 1;
    cpu.putGeneral(rD, pc);
    imm = cpu.signExtendedIMM(imm);
    cpu.putPC(imm);
    msr = cpu.getMSR();
    msr = msr | 0x8;
    cpu.putMSR(msr);
    return cpu_status.JUMP;
  }